Multi-level cell NAND memory can store two bits in one cell; one upper bit and one lower bit stored in corresponding pages, each page typically comprising eight kilobytes of data. All lower bits in one page comprise a lower page, and all upper bits in one page comprise an upper page. In multi-level cell NAND memory, when an upper page is corrupted, the lower page is also corrupted. If programming of one cell fails, both lower bits and upper bits cannot be read out. Multi-level cells require that the lower page must be programmed first, and then the correspondent upper page can be programmed. If programming the upper page fails, the corresponding lower page will also be corrupted, and can't be read out.
Some systems utilize memory mapping for relating logical block addresses to multi-level cell pages when new data is written to improve performance by preventing write operations until multiple writes can be written to multi-level cells in a batch process. In those cases, a power failure during a write operation could result in old data being returned after power is restored.
Consequently, it would be advantageous if an apparatus existed that is suitable for preventing old data from being returned after a power failure in an efficient multi-level cell architecture.